1. Field of the Invention
The present invention relates to a semiconductor device in which a gate is constituted by a plurality of input electrodes, for example, a Neuro transistor of a floating gate type, and a method of operating the semiconductor device.
2. Description of the Related Art
A Neuro device is a device in which a function equivalent to a nerve cell (neuron) constituting the brain, the eyes and the like of a human being is realized by an electric circuit. Specifically, a Neuro device weights a plurality of input signals, respectively, and outputs a predetermined signal when the result of addition of the weighted signals reaches a predetermined value. Such a Neuro device comprises weighting means for weighting the plurality of input signals and a Neuro transistor in which conduction between a source and a drain occurs when the sum of input voltages to a gate constituted by a plurality of input electrodes reaches a predetermined value. The weighting means corresponds to synapses of the nerve cell, which is constituted by, for example, a resistor and a field effect transistor. The Neuro transistor corresponds to the cell body of the nerve cell.
One example of the construction of the Neuro transistor is shown in FIG. 7. This Neuro transistor is referred to as one of a floating gate type. For example, a pair of N.sup.+ -type impurity diffusion layers 2 and 3 corresponding to a source and a drain is formed spaced apart from each other by a predetermined distance on a P-type semiconductor substrate 1. A region therebetween becomes a channel region 4. A gate oxide film 5, a floating gate 6 and an interlayer insulation film 7 are sequentially laminated on the channel region 4. A plurality of input electrodes 11, 12, 13, 14 and 15 to which weighted input signals are respectively applied are formed on the interlayer insulation film 7.
FIG. 3 is an electric circuit diagram showing an equivalent circuit in the vicinity of a gate of the above described Neuro transistor. Specifically, the Neuro transistor corresponds to a series circuit of a capacitor C.sub.OX and a variable capacitor C.sub.M. The capacitor C.sub.OX is constituted by the semiconductor substrate 1, the gate oxide film 5 and the floating gate 6. On the other hand, the variable capacitor C.sub.M is constituted by the plurality of upper electrodes 11, 12, 13, 14 and 15 constituting the gate, the interlayer insulation film 7 and the floating gate 6.
For example, consider a case where a voltage of 0 volt or 5 volts is applied to the respective upper electrodes 11, 12, 13, 14 and 15. In this case, the capacity of the variable capacitor C.sub.M is changed into six types depending on the number of upper electrodes (0 to 5) to which a voltage of 5 volts is applied. Consequently, the coupling ratio of the capacitor C.sub.M to the capacitor C.sub.OX is changed, thereby to make it possible to modulate the potential on the surface of the channel region 4 among six values.
For example, it is assumed that the threshold value of a voltage to be applied to the upper surface of the gate oxide film 5 so as to allow conduction between the impurity diffusion regions 2 and 3 is 3 volts. In this case, when a voltage of 5 volts is applied to the upper electrode 11 and a voltage of 0 volt is applied to the remaining upper electrodes 12, 13, 14 and 15, a substantial applied voltage to the channel region 4 becomes, for example, 1 volt, so that no conduction between the impurity diffusion regions 2 and 3 occurs. On the other hand, when a voltage of 5 volts is applied to each of the upper electrodes 11, 13 and 15 and a voltage of 0 volt is applied to the remaining upper electrodes 12 and 14, a substantial applied voltage to the channel region 4 becomes, for example, 3 volts, so that conduction between the impurity diffusion regions 2 and 3 occurs.
When the sum of the applied voltages to the upper electrodes 11, 12, 13, 14 and 15 is not less than 15 volts, conduction between the impurity diffusion regions 2 and 3 occurs. That is, this transistor has the same function as the cell body of the nerve cell.
If the above described Neuro transistor is used, a five-input NAND gate, for example, can be constituted by one transistor. Consequently, if the Neuro transistor is used to construct an integrated circuit, it is possible to constitute a high-function integrated circuit by a small number of devices.
Although the above described Neuro transistor is effective for the decrease in the number of devices, however, it has a large number of wires. Therefore, if the integrated circuit is constructed using this Neuro transistor, the number of wires is significantly increased, resulting in the increased substrate area.